发明名称 |
Utilization of MACRO power routing area for buffer insertion |
摘要 |
A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver. |
申请公布号 |
US6855967(B2) |
申请公布日期 |
2005.02.15 |
申请号 |
US20020283892 |
申请日期 |
2002.10.30 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
LIU LOUIS CHAO-CHIUAN;CHEN CHIEN-WEN |
分类号 |
H01L23/528;(IPC1-7):H01L27/10;H01L23/52;H01L23/48;H01L23/04 |
主分类号 |
H01L23/528 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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