| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a receiver, etc. capable of processing data synchronously with a transmit side clock signal without a PLL circuit, and realizing the developing time reduction, the miniaturization, a low power consumption and cost reduction. <P>SOLUTION: A transmitter 100 comprises a shift clock circuit 20 and a controller for controlling the shift clock circuit 20. In reception, it writes data in a FIFO memory 12 synchronously with a transmit side clock signal and reads data from the FIFO memory 12 at the same time synchronously with a read clock signal generated by the shift clock circuit 20. If a frequency deviation occurs between the read clock signal and the write clock signal, it controls the shift clock circuit 20 to lower or raise the frequency of the read clock signal when the data quantity in the FIFO memory 12 is below 1/3 its capacity, or over 2/3 the capacity, respectively. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
