发明名称 METHOD AND APPARATUS FOR SHIFTING AT-SPEED SCAN PATTERNS IN A SCAN-BASED INTEGRATED CIRCUIT
摘要 A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus (421), provided at a selected data-rate R1 (421), into a decompressed stimulus (424, 426, 433, 435), driven at a selected data-rate R2 (442), for driving selected scan chains in a scan-based integrated circuit (401). The scan-based integrated circuit (401) contains a high-speed clock CK1 (443), a low-speed clock CK2 (442), a plurality of scan chains (411), ..., (418), each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) (402, 403) and time-division multiplexors (TDMs) (408, 409) for shifting stimuli (421) and test responses (444) in and out of high-speed I/O pads. When applied to the scan-based integrated circuit (401) embedded with one or more pairs of decompressors (404, 405) and compressors (406-407), it can further reduce the circuit's test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division demultiplexors (TDDMs) (402, 403), decompressors (404, 405), compressors (406, 407), and time-division multiplexors (TDMs) (408, 409).
申请公布号 WO2005013037(A2) 申请公布日期 2005.02.10
申请号 WO2004US22298 申请日期 2004.07.30
申请人 SYNTEST TECHNOLOGIES, INC. 发明人 WANG, LAUNG-TERNG (L.-T.);ABDEL-HAFEZ, KHADER, S.;WEN, XIAOQING;SHEU, BORYAU, (JACK);HSU, FEI-SHENG;KIFLI, AUGUSLI;LIN, SHYH-HORNG;WU, SHIANLING;WANG, SHUN-MIIN (SAM);CHANG, MING-TUNG
分类号 G01R31/28;G06F;H04J3/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址