| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory control method and a device for it reducing a waiting time caused by memory access for the speedup of processing by a central processing unit. SOLUTION: A signal generation part 12 detects a stage in which a CPU 2 reads an interruption vector number from an interruption controller 3 according to an address AD on an address bus 6 to generate an address of a ROM 4 accessed by the CPU 2 next according to the interruption vector number outputted to a data bus 7 during the detected stage. The generated address is fed as a previously read address PA to the ROM 4 via a selector 10 before the CPU 2 starts access to the ROM 4. In this process, an output buffer 11 is turned off. Subsequently, when the CPU 2 starts access to the ROM 4, the selector 10 is switched so that the address on the address bus 6 is fed to the ROM 4 while the output buffer 11 is turned on. COPYRIGHT: (C)2005,JPO&NCIPI
|
