发明名称 |
Distribution of architectural state information in a processor across multiple pipeline stages |
摘要 |
Methods and apparatuses for distributing architectural state information in a processor across multiple pipeline stages are described. An architectural value of a register is represented by a historical value added to an update value which is maintained in a non-final pipeline stage. When an instruction requires the architectural value, a calculation is made and that value is inserted into the pipeline for processing. Recovery of both pre- and post-execution architectural state information is made possible by storing both the update value and the operation to take place on that value for each decoded instruction. |
申请公布号 |
US2005033942(A1) |
申请公布日期 |
2005.02.10 |
申请号 |
US20030637417 |
申请日期 |
2003.08.08 |
申请人 |
GOCHMAN SIMCHA;VALENTINE ROBERT;SPIGELMAN RAFAEL;PRIBUSH GREGORY |
发明人 |
GOCHMAN SIMCHA;VALENTINE ROBERT;SPIGELMAN RAFAEL;PRIBUSH GREGORY |
分类号 |
G06F9/30;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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