| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To realize a wide operation range by improving low-speed operation performance while maintaining high-speed operation performance. <P>SOLUTION: A data holding differential logic circuit has a 1st data holding differential couple (FETs 13 and 14, and FETs 28 and 29) of positive feedback constitution, a 2nd data holding differential couple (FETs 15 and 16, and FETs 30 and 31) of negative feedback constitution connected to the 1st data holding differential couple in parallel, and a current weighting differential couple (FETs 17 and 18, and FETs 32 and 33) such that the source joint or emitter joint of the 1st data holding differential couple and 2nd data holding differential couple is connected to the drains or collectors respectively. Then, control signals ST and SC corresponding to an operation speed are inputted to the gates or bases of the current weighting differential couple. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
