发明名称 Zero voltage class AB minimal delay output stage and method
摘要 A class AB output circuit includes a P-channel pullup transistor (M13) having a source coupled to a supply voltage, a drain coupled to an output(10), a gate coupled to respond to an input signal on an input(9), an N-channel pulldown transistor (M1) having a drain coupled to the output, a source coupled to ground, and a gate coupled to respond to the input signal. A first N-channel transistor (M2) has a drain coupled to a gate of the output transistor and the supply voltage by means of a current source (8) and a source coupled to ground by means of a second current source (13). A first diode-connected N-channel transistor (M3), a second diode-connected N-channel transistor (M4), and a first level shifting circuit (17) are coupled in series between ground and a gate of the N-channel transistor, and a current source (7) is coupled between the first supply voltage and the gate of the first N-channel transistor. A second level shifting circuit (18) is coupled between the gate of the pulldown transistor and the source of the first N-channel transistor.
申请公布号 US2005030097(A1) 申请公布日期 2005.02.10
申请号 US20030637434 申请日期 2003.08.08
申请人 IVANOV VADIM V.;SPADY DAVID R. 发明人 IVANOV VADIM V.;SPADY DAVID R.
分类号 H03F3/18;H03F3/21;H03F3/30;H03F3/345;H03F3/45;(IPC1-7):H03F3/18 主分类号 H03F3/18
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