发明名称 |
Etching and plasma treatment process to improve a gate profile |
摘要 |
A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.
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申请公布号 |
US2005032386(A1) |
申请公布日期 |
2005.02.10 |
申请号 |
US20030634001 |
申请日期 |
2003.08.04 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
CHANG MING-CHING;LIN LI-TE;WANG YU-I;CHIU YUAN-HUNG;TAO HUI-JAN |
分类号 |
H01L21/302;H01L21/3213;H01L21/461;H01L21/8238;(IPC1-7):H01L21/302 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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