| 摘要 |
Memory system (100) including a memory matrix (Memory) for storing digital data and processing and controlling means (CPU) destined to interact with the memory matrix in order to read digital data and perform the corresponding operations. <??>Moreover, the system comprises an error detection device (NVMCC) distinct from said processing and controlling means (CPU). This device can access the memory matrix in order to perform an at least partial reading of the locations by detecting the presence of alterations of the digital data stored in them. Moreover, the abovementioned detection device makes it possible either to inhibit the performance of the operations by the processing and controlling means when error detection occurs, or to send to the processing and controlling means a signal indicating the error detected. <IMAGE> |
