| 摘要 |
A programmable logic device includes a memory with user selectable power consumption. During configuration, the memory operates at a relatively high power consumption level and quickly outputs configuration information. During normal operation, the memory selectively operates at the high power level or at a lower power level. The lower power level provides a lower rate of memory access than the high power level. The lower power level may be selected when the user desires to power other areas of the programmable logic device or when the user desires a lower rate of memory access. In this manner, a single memory can serve multiple functions without consuming an excessive amount of power.
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