发明名称 Methods and apparatuses for a ROM memory array having twisted source or bit lines
摘要 Various methods, apparatuses, and systems in which a read only memory is arrayed in a multiple rows and columns. A first column of memory cells is organized into groups of memory cells including a first group of memory cells and a second group of memory cells. A first source line connects to one or more memory cells in the first group of memory cells. The first source line changes its voltage state during a read operation on one or more bit cells in the first group. A second source line connects to one or more memory cells in the second group of memory cells. The second source line maintains its voltage state during the read operation.
申请公布号 US6853572(B1) 申请公布日期 2005.02.08
申请号 US20030377845 申请日期 2003.02.28
申请人 VIRAGE LOGIC CORPORATION 发明人 SABHARWAL DEEPAK
分类号 G11C5/06;G11C7/18;G11C16/24;(IPC1-7):G11C5/06 主分类号 G11C5/06
代理机构 代理人
主权项
地址