发明名称 |
Phase-lock loop having programmable bandwidth |
摘要 |
A phase-locked loop having a programmable loop bandwidth is provided. A PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-correction signal. The PLL further comprises a phase-frequency detector (PFD) coupled to the oscillator and operable to receive a reference signal and to generate the error-correction signal based upon a phase difference between the reference signal and a feedback signal derived from the oscillator signal. The PLL further comprises an error-correction signal suppression circuit coupled to the PFD and operable to control the loop bandwidth of the PLL by periodically enabling the PFD.
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申请公布号 |
US6853252(B2) |
申请公布日期 |
2005.02.08 |
申请号 |
US20020264360 |
申请日期 |
2002.10.04 |
申请人 |
INTERSIL CORPORATION |
发明人 |
DICKMANN MARK |
分类号 |
G06F1/10;G06F1/26;H03K5/00;H03K23/66;H03L7/07;H03L7/089;H03L7/107;H03L7/183;(IPC1-7):H03L7/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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