发明名称 |
Power-up detection circuit with low current draw for dual power supply circuits |
摘要 |
A power monitor circuit for notifying processing circuits operating from a first power supply (VDD) that a second power supply (VDDIO) is powered up. VDDIO is greater than VDD. The power monitor circuit comprises: 1) a voltage divider circuit coupled between the second power supply and ground having an output node that goes high when the second power supply is powered up; and 2) an odd number of serially connected inverters operating from the first power supply. An input of a first serially connected inverter is connected to the voltage divider circuit output node. An output of the last serially connected inverter produces a status signal that is the inverse of the voltage divider circuit output node. The status signal is an input to the voltage divider circuit that minimizes the voltage divider circuit-s current consumption when the second power supply is ON, while maintaining the status signal value.
|
申请公布号 |
US6853221(B1) |
申请公布日期 |
2005.02.08 |
申请号 |
US20010037180 |
申请日期 |
2001.10.23 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
WERT JOSEPH D. |
分类号 |
H03K17/22;H03L7/00;(IPC1-7):H03L7/00 |
主分类号 |
H03K17/22 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|