发明名称 |
System and method of acquiring delay, setup and hold values for integrated circuit cells |
摘要 |
The method of the present invention acquires delay, setup and hold values that appropriately reflect the timing characteristics of an integrated circuit represented by a cell file. A data and clock input slope pair is selected and the data setup time value is swept with respect to the clock. For each setup value a corresponding hold value is determined for functional failure. Then for each setup and hold value pair a delay value is ascertained. In one exemplary implementation optimal delay, setup and hold values are determined and utilized to facilitate higher frequency designs using the same physical cell layout library.
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申请公布号 |
US6854102(B1) |
申请公布日期 |
2005.02.08 |
申请号 |
US20020229527 |
申请日期 |
2002.08.27 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
MAHESHWARI DINESH |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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