发明名称 Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
摘要 Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be "bottomless," thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.
申请公布号 US6852635(B2) 申请公布日期 2005.02.08
申请号 US20030731656 申请日期 2003.12.08
申请人 INTERUNIVERSITAIR NIZROELECMICA;ASM INTERNATIONAL NV 发明人 SATTA ALESSANDRA;MAEX KAREN;ELERS KAI-ERIK;SAANILA VILLE ANTERO;SOININEN PEKKA JUHA;HAUKKA SUVI P.
分类号 C23C16/02;C23C16/04;C23C16/08;C23C16/32;C23C16/44;C23C16/455;C30B25/02;H01L21/205;H01L21/285;H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/302;H01L21/461 主分类号 C23C16/02
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