发明名称 |
Method of mapping logic failures in an integrated circuit die |
摘要 |
A method of mapping logic failures in an integrated circuit die includes steps of: (a) generating a navigation map of test paths for an integrated circuit die; (b) selecting a grid spacing to define a grid map of cell locations from the navigation map for each of the test paths; and (c) calculating a value for each of the cell locations wherein the value is representative of the difference between a total number of the test paths intersecting each of the cell locations and a failed number of the test paths intersecting each of the cell locations.
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申请公布号 |
US2005028115(A1) |
申请公布日期 |
2005.02.03 |
申请号 |
US20030628986 |
申请日期 |
2003.07.28 |
申请人 |
WHITEFIELD BRUCE;COWAN JOSEPH |
发明人 |
WHITEFIELD BRUCE;COWAN JOSEPH |
分类号 |
G01R31/3193;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/3193 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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