发明名称 Semiconductor memory device
摘要 A reading circuit of a memory cell includes a plurality of reference cells each having at least one of a plurality of possible states of the memory cell, a first pre-sense circuit for supplying current to the memory cell and outputting a first output voltage according to a storage state of the memory cell, a plurality of second pre-sense circuits for supplying currents to the plurality of reference cells and outputting second output voltages according to storage states of the reference cells, and a sense amplifier. The sense amplifier is constructed so that one of differential input stages of a differential amplifier is divided in parallel into the same number of pieces as that of the reference cells, the second output voltages of the plurality of second pre-sense circuits are supplied to the divided inputs, and the first output voltage of the first pre-sense circuit is supplied to the other differential input stage.
申请公布号 US2005024967(A1) 申请公布日期 2005.02.03
申请号 US20040901642 申请日期 2004.07.28
申请人 SHARP KABUSHIKI KAISHA 发明人 MATSUOKA NOBUAKI
分类号 G11C16/06;G11C7/02;G11C7/06;G11C13/00;G11C16/04;G11C16/28;(IPC1-7):G11C7/02 主分类号 G11C16/06
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