| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an image forming apparatus which reduces a system down time to the utmost, and a clock control apparatus. <P>SOLUTION: Since an input clock signal to a PLL circuit is used as a system clock signal when a PLL error occurs, the frequency of occurrence of system down can be reduced although the operation performance of the system deteriorates, thereby realizing a system having higher operability. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
