| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce remarkably an error rate in a bit synchronizing circuit by preventing excessive follow-up to a jitter included in input data. <P>SOLUTION: A semiconductor integrated circuit device includes a phase comparing circuit in the bit synchronizing circuit and having a majority circuit 3b. The majority circuit 3b counts UPO/DNO signal of a phase comparison result of phase comparison by an UPO counter 24, a DNO counter 26 for a certain period, and determines the number of counts by a magnitude determination circuit 28. The magnitude determination circuit 28 outputs an UP signal if there is much UPO signal, a DN signal if there is much DNO signal or a FIX signal if the UPO signal is the same as the DNO signal. Thus, since excessive follow-up to the jitter included in the input data, etc. can be prevented, the error rate in the bit synchronization can be remarkably reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
