发明名称 CIRCUIT AND METHOD FOR PACKET TRANSFER CONTROL
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a packet transfer control circuit with a simple hardware configuration for performing band control on each of a plurality flows of packets, and realizing priority control simultaneously. <P>SOLUTION: The packet transfer control circuit comprises a class setting unit 133, an output queue unit 140, and an arrival rate update unit 150. The class setting unit 133 compares a flow setting information for a flow read from a flow setting information storage unit 120 with an arrival rate for the flow from a rate computing unit 132 based on the flow identified by a flow identifying unit 110, and sets up a class of the flow, to which a packet belongs, in unit of the packet. The output queue unit 140 controls output sequence for a plurality of the packets based on the class of the flow, to which the packets belong, established by the class setting unit 133. The arrival rate update unit 150 updates the arrival rate information for the flow with a predetermined timing, based on residual data amount from the output queue unit 140 and the packet arrival rate information on the flow setting information. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2005033673(A) 申请公布日期 2005.02.03
申请号 JP20030272879 申请日期 2003.07.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KANAZAWA TAKESHI
分类号 H04L12/801;H04L12/813;H04L12/823;H04L12/865;H04L12/911;H04L29/06;(IPC1-7):H04L12/56 主分类号 H04L12/801
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