发明名称 VIDEO DECODING OUTPUT DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To guarantee a real-time performance by varying computational complexity of filter processing and sufficiently utilizing the computation resources when the computation complexity in decoding using a restoration processor is changed in a video decoding output device. <P>SOLUTION: In the video decoding output device, a loading state relating to the decoding in an image code stream decoding means 300 is detected from the values of a vertical synchronizing signal, a horizontal synchronizing signal and a signal V-Counter 703 counted up by falling of the horizontal synchronizing signal that is time information synchronized to the horizontal synchronizing signal, and is initialized to 0 each time the vertical synchronizing signal falls twice by a video synchronizing signal generating means 700. Further, when a load on the image code stream decoding means 300 is less, the number of filter taps in a filter processing means 500 is set high by this video decoding output device, so that the computation complexity of the filter processing means 500 is increased and when the load on the image code stream decoding means is heavy, the number of filter taps in the filter processing means 500 is set low. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2005033724(A) 申请公布日期 2005.02.03
申请号 JP20030273615 申请日期 2003.07.11
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 WATANABE SHINICHI;SHIBATA TADASHI;NISHIO TAKATOSHI
分类号 H04N19/117;H04N7/01;H04N7/24;H04N19/00;H04N19/134;H04N19/14;H04N19/156;H04N19/423;H04N19/44;H04N19/70;H04N19/80;(IPC1-7):H04N7/24 主分类号 H04N19/117
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