发明名称 |
Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect |
摘要 |
In a method and apparatus for controlling a dual-slope integrator circuit, a reset signal is provided to a reset input of the integrator circuit to maintain a reset state of an integrating capacitor for a predetermined reset time period in response to an original input signal. A delayed input signal is simultaneously generated by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period. With reference to the original input signal and the delayed input signal, a trigger signal is provided to an integrator input of the integrator circuit for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.
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申请公布号 |
US2005024120(A1) |
申请公布日期 |
2005.02.03 |
申请号 |
US20030748580 |
申请日期 |
2003.12.30 |
申请人 |
CHANG TSIN-YUAN;HSIAO MING-JUN;HUANG JING-RENG |
发明人 |
CHANG TSIN-YUAN;HSIAO MING-JUN;HUANG JING-RENG |
分类号 |
G06F5/00;G06G7/18;G06G7/186;H03K4/00;H03K4/06;H03K5/1534;(IPC1-7):G06G7/18 |
主分类号 |
G06F5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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