Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines

摘要

A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage VCC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead.