DMA controller with bus occupation time limitation and sets of DMA parameters for a plurality of logical processors

摘要

The present invention provides a DMA transfer controller including: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapsed time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapsed time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors in a prescribed sequence. <IMAGE>