发明名称 |
Apparatus for issuing command for high-speed serial interface |
摘要 |
In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU. <IMAGE> |
申请公布号 |
EP1253520(A3) |
申请公布日期 |
2005.02.02 |
申请号 |
EP20020008865 |
申请日期 |
2002.04.19 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
ISHIMURA, ISAMU;TABIRA, YOSHIHIRO |
分类号 |
G06F13/12;G06F13/38 |
主分类号 |
G06F13/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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