发明名称
摘要 PROBLEM TO BE SOLVED: To attain flow rate integration processing in a low frequency clock CPU driven by a battery with low power consumption and high precision without operating any miss count even when the frequencies of a flow rate signal are made high. SOLUTION: Flow rate signal pulses in a number proportional to a fluid flow rate from a flow rate signal outputting means 2 are counted by a counter 11, and when a residual number C of pulses in the counter in each constant period is a prescribed number n or more, flow rate values for the n input pulses are integrated as an integrated value, and the n pulses are subtracted from the counter 11. When the residual number 9 of pulses is 1-less than the prescribed number n, a flow rate value for one input pulse is integrated as an integrated value, and one pulse is subtracted from the counter.
申请公布号 JP3616261(B2) 申请公布日期 2005.02.02
申请号 JP19980290239 申请日期 1998.10.13
申请人 发明人
分类号 G01F15/075;H03K21/40;(IPC1-7):G01F15/075 主分类号 G01F15/075
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