| 摘要 |
<p>PURPOSE: To reliably prevent the erase of a memory cell due to an input failure or misrecognition by invalidating the erase command inputted previously when no erase command is inputted within a preset period after the second time. CONSTITUTION: When a first erase command is inputted, the command signal 25 of a data bus 9 is brought into the H-level by the use of a decoder 21 and a H-level signal 29 is inputted into a time count start control circuit 41 from a latch circuit 23 to start the count of a timer 43. When the second input is an erase command, the latch signals 29, 30 are brought into the H-level to erase the content of the memory cell by the use of an erase signal 32. When the second input is not an erase command, the command signal 25 is brought into the L-level to continue the count of the timer 43. When the count overflows, the signal 44 is brought into the H-level to initiate a control circuit 41 and to suspend the count of the timer 43. At the same time, a reset signal 46 releases the latch of the latch circuit 23 to finish the erase mode.</p> |
