发明名称 Method for manufacturing semiconductor device
摘要 A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.
申请公布号 US6849550(B2) 申请公布日期 2005.02.01
申请号 US20020190756 申请日期 2002.07.09
申请人 SANYO ELECTRIC CO. LTD. 发明人 ICHIHASHI YOSHINARI;IKEDA NORIHIRO;GOTOU TAKASHI;USUI RYOUSUKE;FUJISHIMA TATSUYA
分类号 H01L21/28;H01L21/768;H01L23/522;(IPC1-7):H01L21/302 主分类号 H01L21/28
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