发明名称 |
Method for semiconductor gate line dimension reduction |
摘要 |
To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
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申请公布号 |
US6849530(B2) |
申请公布日期 |
2005.02.01 |
申请号 |
US20020334337 |
申请日期 |
2002.12.30 |
申请人 |
ADVANCED MICRO DEVICES |
发明人 |
BONSER DOUGLAS J.;PLAT MARINA V.;YANG CHIH YUH;BELL SCOTT A.;DAKSHINA-MURTHY SRIKANTESWARA;FISHER PHILIP A.;LYONS CHRISTOPHER F. |
分类号 |
H01L21/28;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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