METHOD OF DESIGNING TEST PATTERN FOR BLOCKING GATE TO REDUCE NUMBER OF UNNECESSARY PROCESSES

摘要

PURPOSE: A method of designing a test pattern for blocking a gate is provided to reduce number of unnecessary processes by using a gate oxide layer instead of an oxide layer. CONSTITUTION: A P-well(212) is formed on a semiconductor substrate(210). A gate is formed on the semiconductor substrate including the P-well. A threshold voltage ion implantation process is performed on the semiconductor substrate. A poly layer(216) is formed on the gate. An NM ion implantation process is performed on the semiconductor substrate. A lightly-doped drain spacer is formed on a lateral part of the gate. An N+ ion implantation process is performed on the semiconductor substrate.