发明名称 METHOD FOR DESIGNING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce man-hours in layout design, and to largely shorten a layout design period by efficiently and automatically performing the layout of respective cells. SOLUTION: Low order layout information constituted of coordinate data, layout order and mirror information is inputted to each primitive cell 1 by a circuit graphic editor. The low order layout information and an instance name are fetched in a layout editor tool, and the primitive cells 1 are automatically arrayed based on the low order layout information so that a circuit cell 2 can be formed. Afterwards, high order layout information constituted of coordinate data, cell column numbers, layout order, mirror information and rotation information is inputted to the circuit cell 2 by a circuit graphic editor tool. The high order layout information and the instance name are automatically fetched in the layout editor tool, and the circuit cells 2 are automatically arranged based on the high order layout information so that an indirect peripheral block 3 can be formed. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005025499(A) 申请公布日期 2005.01.27
申请号 JP20030190100 申请日期 2003.07.02
申请人 RENESAS TECHNOLOGY CORP 发明人 NAKADA KENJI;KITAJIMA HIDENORI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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