| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout method by which area efficiency is improved by simplifying wiring of a data transmission route, a clock transmission route, etc. for facilitating layout work while securing fast operation in an integrated circuit using an SFQ circuit in particular. SOLUTION: P is set to the position of the junction of a clock,αto the position of the logic cell of a poststage (second logic cell), andβto the position of the logic cell of a prestage (first logic cell). A condition (1) is that a virtual rectangle (including a square) where P andαare positioned at vertexes opposing each other across a diagonal line is supposed, andβis arranged inside of the rectangle. A condition (2) is that a route from P toα, a route from P toβand a route fromβtoαare selected to be respectively a Manhattan distance. Then the positions and routes of P,αandβare decided so as to satisfy the conditions (1) and (2). By layout like this, wiring is simplified while keeping fast operation, and the area efficiency is improved. COPYRIGHT: (C)2005,JPO&NCIPI
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