发明名称 Method for analyzing fail bit maps of wafers
摘要 A method of detecting a wafer failure includes extracting the wafer ID of a target wafer in the target lot from the lot ID, extracting the location information of a failure in the target wafer, calculating a to-be-quantified first wafer feature amount for unevenness of a wafer failure distribution, calculating a first lot feature amount for each target lot, extracting a fabrication process for the target lot and a fabrication apparatus, carrying out a significant test for the fabrication apparatus used in each fabrication process, and detecting the fabrication apparatus with a significant difference as a first abnormal apparatus.
申请公布号 US2005021303(A1) 申请公布日期 2005.01.27
申请号 US20040865927 申请日期 2004.06.14
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MATSUSHITA HIROSHI;KADOTA KENICHI
分类号 H01L21/66;G06F11/30;G11C29/00;H01L21/02;(IPC1-7):G06F11/30 主分类号 H01L21/66
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