Bit-detection arrangement and apparatus for reproducing information

摘要

Described is an invention relating to a bit-detection arrangement able to convert an analog signal (AS) into a digital signal (DS). The analog signal (AS) is fed to a quantizer (11). After the quantizer (11) the output signal S1 is fed to a phase detector PD1 (12). Also samples are taken of the output signal S1. The output signal PH2 (of the phase detector PD1 (12) is dependent on the phase difference between the output signal S1 and the clock signal C2. If the frequency of the clock signal C2 is approximately equal to the frequency of the output signal S1 then the output signal PH2 of the phase detector PD1 (12) varies slowly. The analog to digital converter ADC (13) can therefore sample the output at a slow rate, dictated by the clock signal C1. The clock signal C1 is derived from C2 by dividing clock signal C2 by a factor n, whereby n is greater than one. To obtain the phase differences at clock periods of clock signal C2, the processed signal PrS of the analog to digital converter ADC (13) is interpolated. This can be done in different ways. A special embodiment comprises a digital phase locked loop DPLL (2) with discrete time oscillators. The obtained phase differences are used by the bit decision unit (3) to output the samples.