| 摘要 |
PROBLEM TO BE SOLVED: To limit current consumption of a reference voltage generation circuit without requiring a large circuit pattern. SOLUTION: A diode-connected PMOS(p-channel MOS transistor) 11 and a register 12 are connected in series between potential VCC of 3V e.g. and potential VSS of 0V to generate constant voltage from the PMOS 11. A PMOS 13 constituting a current mirror is connected to the PMOS 11 and the PMOS 13 is connected to potential VEE of -15 V through a diode-connected NMOS 14. Therefore, reference voltage VREF1 is outputted from the drain of the NMOS 14. An NMOS 15 constituting a current mirror is connected to the NMOS 14 and the NMOS 15 is connected to potential VDD of +15 V through a diode-connected PMOS 16. Therefore, reference voltage VREF2 is outputted to the drain of the PMOS 16. Since voltage applied to the current limiting resistor 12 is low, the current can be sufficiently limited even when a resistance value (circuit pattern) is small. COPYRIGHT: (C)2005,JPO&NCIPI
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