WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD FOR FABRICATING AND USING THE SAME

摘要

First, second, and third packaged semiconductor devices (a wafer-level chip scale package) are described. The first packaged semiconductor device contains no UBM between a chip pad and an RDL pattern. The first device contains only a single non-polymeric insulation layer between the RDL pattern and the solder bump, where the insulation layer does not need high temperature curing processes and so does not induce thermal stresses into the device. Manufacturing costs for the first device are diminished by eliminating the UBM between the chip pad and the RDL pattern. The second packaged semiconductor device (a second wafer-level chip scale package) contains an adhesive film containing conductive particles sandwiched between a chip with Cu-based stud bumps and a substrate containing a bond pad. Some conductive particles are sandwiched between the stud bump and bond pad to create a conductive path. The second device is manufactured without the steps of dispensing solder and reflowing the solder and can optionally eliminate the use of a redistribution trace. Using such a configuration increases the reliability of the second wafer-level chip scale package. The third packaged semiconductor device (a third wafer-level chip scale package) contains a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.