发明名称 |
Method of finding critical nets in an integrated circuit design |
摘要 |
A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an approximate delay for each net in the integrated circuit design wherein the approximate delay includes an estimate of crosstalk delay; (c) identifying timing critical nets from the calculated delay for each net in the integrated circuit design; (d) calculating a corresponding exact delay for each of the timing critical nets; (e) replacing the approximate delay calculated for each of the timing critical nets with the corresponding exact delay to generate a corrected set of net delays for the integrated circuit design; and (f) generating as output the corrected set of net delays for the integrated circuit design.
|
申请公布号 |
US2005022145(A1) |
申请公布日期 |
2005.01.27 |
申请号 |
US20040924531 |
申请日期 |
2004.08.23 |
申请人 |
TETELBAUM ALEXANDER;AL-DABAGH MAAD A. |
发明人 |
TETELBAUM ALEXANDER;AL-DABAGH MAAD A. |
分类号 |
G06F9/45;G06F17/50;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|