| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock adjustment circuit and a clock adjusting method capable of suppressing the jitters in a communication terminal side, etc., and continuing communication even when the adjustment width of the clock becomes large for synchronizing the gateway device, etc. <P>SOLUTION: Transmission delay t1 to t0 occurs between an external clock and a main signal. Then, a delay time (hereinafter called required delay time) corresponding to t7 to t1 is given to the main signal to apply phase synchronization to the external clock. However, if the required delay time is given at a time, there is a possibility that a mobile terminal device, etc., connected to this device can not follow. Therefore, clock adjustment is divided into the following steps: after 0msec; after 5msec; after 10msec to after 30msec, being gradually carried out. That is, by gradually increasing or reducing the delay time to be given in each step, the clock adjustment for the required delay time is finally completed. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
