发明名称 Processing method for data in a mixed-timing system, whereby a third clock signal is formed from the second data processing clock signal by application of a delay and a test signal is generated based on signal flank positions
摘要 <p>Method for processing data from a data source (10) that operates using a first clock signal (CLK1) at a rate set by a second clock signal (CLK2) whereby: the second clock signal is delayed by a preset delay time (td1) to provide a third clock signal (CLK21) which is then used to process data; the temporal position of a given flank of the first signal is evaluated referenced to a first flank of the third clock signal; and a test signal (CS) is provided that takes a first or second value dependent on whether flanks of the first and third clock signals lie within a predefined time window. The invention also relates to a corresponding circuit arrangement for generating a test signal.</p>
申请公布号 DE10330328(A1) 申请公布日期 2005.01.27
申请号 DE2003130328 申请日期 2003.07.04
申请人 INFINEON TECHNOLOGIES AG 发明人 AICHRIEDLER, LEO;PICAUD, BENOIT
分类号 G06F1/12;G06F5/08;H04L1/24;(IPC1-7):H04L1/24 主分类号 G06F1/12
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