| 摘要 |
A demodulator and a demodulation method are designed so as to reduce the load of a CPU. A host CPU controls a digital demodulation circuit, an error correction circuit, a transport circuit and an MPEG decoder through a bus. The host CPU outputs a control signal to a format conversion circuit via a CPU interface when it instructs a tuner to perform tuning. The format conversion circuit converts the format of this control signal into a 3-wire format and outputs the converted signal to a frequency divider of the tuner.
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