| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve problems in a dynamic fault test method such that power noises are generated due to voltage drop of the power and accurate test results cannot be obtained because a time interval between a release clock and capture clock and a interval of changes in a logical value are short. <P>SOLUTION: A circuitry which divides a circuit to be tested into a plurality of groups by utilizing a clock control circuit which divides one clock signal into a plurality of signals and controls propagation and cutoff of the signals. By utilizing the circuitry, a dynamic fault test as one test step is limitedly conducted to some of the groups of the circuit to be tested. Therefore, by conducting the test step several times, the dynamic fault test can be conducted to the all of the circuit to be tested. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
