发明名称 TIMING SIGNAL GENERATING CIRCUIT AND SIGNAL RECEIVING CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a timing signal generating circuit capable of highly accurately generating a plurality of timing signals having a predetermined phase difference with a simple configuration, and a signal receiving circuit provided with the timing signal generating circuit. <P>SOLUTION: A resistor value control unit 24 outputs a resistance control signal for controlling weight of composite for each of signals in phase-compositing a plurality of clock signals Va, Vax, Vb, Vbx having a plurality of kinds of phases. Upon receiving the plurality of clock signals respectively, transconductance amplifiers 22a-22d output a plurality of current outputs I1-I4 whose amplitudes are controlled by allowing resistors R1-R4 to change the resistances according to the resistance control signals. An output terminal OUT connected to the outputs OUT1 of the plurality of transconductance amplifiers 22a-22d sums the current outputs I1-I4 outputted from the transconductance amplifiers 22a-22d to output a phase-composited signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2005026760(A) 申请公布日期 2005.01.27
申请号 JP20030187074 申请日期 2003.06.30
申请人 FUJITSU LTD 发明人 CHIBA TAKAYA;ISHIDA HIDEKI
分类号 G06F1/12;H03F3/45;H03G3/10;(IPC1-7):H03G3/10 主分类号 G06F1/12
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