METHOD FOR FORMING METAL INTERCONNECTION OF SEMICONDUCTOR DEVICE BY DUAL DAMASCENE PROCESS TO PREVENT METAL INTERCONNECTION FROM BEING DETERIORATED BY DEFECT LIKE WATER MARK AND PREVENT INNER CAPACITANCE FROM BEING INCREASED BY ETCH STOP LAYER

摘要

PURPOSE: A method for forming a metal interconnection of a semiconductor device by a dual damascene process is provided to prevent a metal interconnection from being deteriorated by a defect like water mark and prevent inner capacitance from being increased by an etch stop layer by avoiding forming water mark in an interlayer dielectric even if an etch stop layer with a high dielectric constant is not formed on the interlayer dielectric. CONSTITUTION: An interlayer dielectric(106) is formed by using a low dielectric material on a semiconductor substrate(100) in which the first diffusion barrier layer(102), an insulation layer(103) including a lower metal interconnection(104) and the second diffusion barrier layer(105) are sequentially formed. By using a photoresist layer, the interlayer dielectric and the second diffusion barrier layer are patterned to form a via hole. An organic ARC(anti-reflective coating) is deposited on the resultant structure to fill the via hole. A trench portion is defined by using a photoresist layer, and the organic ARC and the interlayer dielectric are etched by a predetermined depth according to the photoresist layer pattern so as to form a trench. The organic ARC remaining on the resultant structure is removed. A metal layer is deposited to be filled in the via hole and the trench so that an upper metal interconnection is formed. After the upper metal interconnection is planarized, an oxygen treatment is performed to change the interlayer dielectric to be hydrophilic.