发明名称 METHOD FOR FORMING METAL INTERCONNECTION OF SEMICONDUCTOR DEVICE TO REDUCE QUANTITY OF POLYMER GENERATED IN PROCESS FOR FORMING VIA HOLE AND METAL INTERCONNECTION TRENCH
摘要 PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to reduce the quantity of polymer generated in a process for forming a via hole and a metal interconnection trench by eliminating a photoresist pattern, a BARC(bottom anti-reflective coating) and an etch stop layer by a wet etch process. CONSTITUTION: The first etch stop layer(14), the second interlayer dielectric(16), the second etch stop layer and the third interlayer dielectric are sequentially formed on the first interlayer dielectric(10) in which a metal interconnection is filled. A photoresist pattern for defining a via hole is formed in a predetermined region of the third interlayer dielectric. After even the first etch stop layer is etched to form a via hole by using the first photoresist pattern as an etch mask, the first photoresist pattern is eliminated. A BARC is formed on the resultant structure. The second photoresist pattern for defining a metal interconnection is formed in another predetermined region of the BARC layer. After even the second etch stop layer is etched to form a metal interconnection trench by using the second photoresist pattern as an etch mask, the second photoresist pattern and the BARC are removed by the first wet etch process. The first etch stop layer is etched by the second wet etch process using the second interlayer dielectric as an etch mask. A cleaning process is performed on the resultant structure by the third wet etch process.
申请公布号 KR20050009941(A) 申请公布日期 2005.01.26
申请号 KR20030049469 申请日期 2003.07.18
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHO, IHL HYUN
分类号 H01L21/28;H01L21/302;H01L21/306;H01L21/311;H01L21/461;H01L21/768;(IPC1-7):H01L21/28 主分类号 H01L21/28
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