发明名称 METHOD FOR FORMING MIM CAPACITOR BY DAMASCENE PROCESS TO PREVENT UPPER AND LOWER METAL LAYERS FROM BEING SHORT-CIRCUITED AND CONTROL GENERATION OF LEAKAGE CURRENT
摘要 PURPOSE: A method for forming an MIM(metal insulator metal) capacitor by a damascene process is provided to prevent upper and lower metal layers from being short-circuited and control generation of a leakage current by depositing a compound made of a metal component on the sidewall of an insulator such that the metal component is formed by etching the upper metal layer. CONSTITUTION: The first IMD(intermetal dielectric)(102) is patterned to be predetermined type on an underlying substrate(100). After a patterning process is performed by using the patterned first IMD layer as a mask, a lower metal layer(106) is deposited. The lower metal layer is planarized by a CMP(chemical mechanical polishing) process. An insulation layer(108) and the second IMD layer(110) are sequentially deposited. A patterned photoresist layer of a predetermined type is deposited on the second IMD layer. By using the patterned photoresist layer as a mask, the second IMD layer is etched until the upper surface of the insulation layer is exposed. After an upper metal layer(114) is deposited, the upper metal layer is planarized by a CMP process. The third IMD layer(116) is formed on the planarized upper metal layer and the second IMD layer. A contact hole(120) is formed to electrically connect the upper metal layer with the lower metal layer.
申请公布号 KR20050009796(A) 申请公布日期 2005.01.26
申请号 KR20030048867 申请日期 2003.07.16
申请人 MAGNACHIP SEMICONDUCTOR, LTD. 发明人 JUNG, SUK WON
分类号 H01L21/8242;(IPC1-7):H01L21/824 主分类号 H01L21/8242
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