发明名称 |
Dynamic instruction set augmentation and multiprocessor synchronization using electronically reconfigurable logic arrays |
摘要 |
<p>An apparatus is disclosed for integrating a general purpose processor with one or more electronically reconfigurable logic arrays so that a subset of the general purpose processor instruction set encodings (opcodes) may control functionality implemented by a reconfigurable logic block analogous to operations implemented by fixed functionality execution units conventionally incorporated within a processor. <IMAGE></p> |
申请公布号 |
EP1501009(A1) |
申请公布日期 |
2005.01.26 |
申请号 |
EP20040014944 |
申请日期 |
1998.10.21 |
申请人 |
FTL SYSTEMS INC. |
发明人 |
WILLIS, JOHN C.;NEWSHUTZ, ROBERT N. |
分类号 |
G06F11/28;G06F9/26;G06F9/38;G06F9/44;G06F9/45;G06F9/50;G06F15/78;G06F17/50;(IPC1-7):G06F9/44 |
主分类号 |
G06F11/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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