发明名称 Floating point divide and square root processor
摘要 An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]-Sj+1*D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, Sj+1 is the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]-2S[j]Sj+1, where W[j] is the estimated partial remainder and Sj+1 is the estimated result generated during the current iteration, j. A shift register shifts the value of the estimated result, Sj+1, to generate -Sj+1<2>.2<-(j+1)>, which is summed with the result from the first summing device to generate the estimated partial remainder for the square root mode.
申请公布号 US6847985(B1) 申请公布日期 2005.01.25
申请号 US20010927139 申请日期 2001.08.10
申请人 LSI LOGIC CORPORATION 发明人 GUPTA GAGAN V.;YU MENGCHEN
分类号 G06F7/38;G06F7/552;(IPC1-7):G06F7/38 主分类号 G06F7/38
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