METHOD FOR FABRICATING DRAM CELL WITH PLANAR CAPACITOR STRUCTURE OF LOW COUPLING NOISE TO INCREASE SENSING MARGIN OF SENSE AMPLIFIER

摘要

PURPOSE: A method for fabricating a DRAM(dynamic random access memory) cell with a planar capacitor structure of low coupling noise is provided to increase a sensing margin of a sense amplifier by intercepting bitline coupling noise without an additional process. CONSTITUTION: A structure of a gate(112) and a planar capacitor(114) is formed on a silicon substrate(100). An interlayer dielectric(118) is formed on the silicon substrate including the structure of the gate and the planar capacitor. A metal contact is formed between the gates. A bitline is formed on the metal contact. An insulation layer(126) between interconnections is formed on the silicon substrate having the bitline. After a via hole is formed between the bitlines on the insulation layer between the interconnections, the via hole is filled with a metal layer to form a via contact(130). A metal interconnection(132) is formed on the via contact. The metal interconnection is connected to the ground.