METHOD FOR FORMING GATE BY DAMASCENE METHOD TO REDUCE SHEET RESISTANCE

摘要

PURPOSE: A method for forming a gate by a damascene method is provided to reduce sheet resistance by guaranteeing a silicide region of a broader structure as compared with a conventional technology. CONSTITUTION: An oxide layer, a BARC(bottom anti-reflective coating) and a photoresist layer are sequentially formed on a silicon substrate(100). The oxide layer is patterned by a dry etch process using plasma. After the photoresist layer and the BARC are eliminated, a gate oxide layer(110) is deposited by a thermal oxide process. A polysilicon layer(112) of about 1800 angstroms is formed. A nitride layer of about 1500 angstroms is formed. The nitride layer to the polysilicon layer are planarized by a CMP(chemical mechanical polishing) process using selectivity of the polysilicon layer and the nitride layer and are planarized by a CMP process using selectivity of the polysilicon layer and the oxide layer. The planarized nitride layer is removed by using H3PO4. A spacer(124) is formed. A Co/TiN layer(126) is deposited. A plasma etch process is performed to eliminate the oxide layer in a region except a region to be salicidized. The first and second RTP's(rapid thermal processes) are performed.