发明名称 |
Method and apparatus for verification of memories at multiple abstraction levels |
摘要 |
This invention relates to method and apparatus for verification of circuit designs containing memories. At a register transfer abstraction level, verification of a circuit design requires showing that the register transfer language (RTL) abstraction of the design is logically equivalent to the design implementation represented at the logic (e.g., gate and/or flip-flop) and/or the transistor (e.g. implementation verification) abstraction levels, as well as logic simulation of the design RTL embedded in a system-level test bench for verification at the system-abstraction level.
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申请公布号 |
US6848084(B1) |
申请公布日期 |
2005.01.25 |
申请号 |
US20020327608 |
申请日期 |
2002.12.20 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
PANDEY MANISH;HINES MITCHELL W.;LIN CHIH-CHANG |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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